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integrated silicon solution, inc. 1 rev. l 09/06/12 copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. IS61LPS51218A, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636a features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? burst sequence control using mode input ? three chip enable option for simple depth ex - pansion and address pipelining ? common data inputs and data outputs ? auto power-down during deselect ? single cycle deselect ? snooze mode for reduced-power standby ? jtag boundary scan for pbga package ? power supply lps: v dd 3.3v + 5%, v ddq 3.3v/2.5v + 5% vps: v dd 2.5v + 5%, v ddq 2.5v + 5% ? jedec 100-pin tqfp, 119-ball pbga, and 165-ball pbga packages ? lead-free available description the issi is61lps/vps25636a, is61lps25632a, is64lps25636a and is61lps/vps51218a are high- speed, low-power synchronous static rams designed to provide burstable, high-performance memory for com - munication and networking applications. the is61lps/ vps25636a and is64lps25636a are organized as 262,144 words by 36 bits. the is61lps25632a is organized as 262,144 words by 32 bits. the is61lps/ vps51218a is organized as 524,288 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. the byte write operation is performed by using the byte write enable ( bwe ) input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be gener - ated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence or - der, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left foating. 256k x 36, 256k x 32, 512k x 18 9 mb synchronous pipelined, single cycle deselect static ram september 2012 fast access time symbol parameter 250 200 166 units t kq clock access time 2.6 3.1 3.5 ns t kc cycle time 4 5 6 ns frequency 250 200 166 mhz
2 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a block diagram 18/19 binary counter gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register ce d clk q dq(a-d) byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw(a-d) x18: a,b x32/x36: a-d ce ce2 ce2 256kx32; 256kx36; 512kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 2/4/8 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a power down zz
integrated silicon solution, inc. 3 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a bottom view bottom view 165-pin bga 165 -ball, 13x15 mm bga 1mm ball pitch, 11x15 ball array 119-pin bga 119-ball, 14x22 mm bga 1mm ball pitch, 7x17 ball array
4 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 119 bga package pin configuration- 256k x 36 (top view) pin descriptions 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc ce2 a adsc a a nc c nc a a v dd a a nc d dqc dqpc vss nc vss dqpb dqb e dqc dqc vss ce vss dqb dqb f v ddq dqc vss oe vss dqb v ddq g dqc dqc bwc adv bwb dqb dqb h dqc dqc vss gw vss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd vss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd vss bwe vss dqa v ddq n dqd dqd vss a 1 * vss dqa dqa p dqd dqpd vss a 0 * vss dqpa dqa r nc a mode v dd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 synchronous chip select bw x (x=a-d) synchronous byte write controls bwe byte write enable symbol pin name oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqd data inputs/outputs dqpa-pd output power supply v dd power supply v ddq output power supply vss ground note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired.
integrated silicon solution, inc. 5 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 119 bga package pin configuration 512k x 18 (top view) pin descriptions note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 a v ddq a a adsp a a v ddq b nc ce2 a adsc a a nc c nc a a v dd a a nc d dqb nc vss nc vss dqpa nc e nc dqb vss ce vss nc dqa f v ddq nc vss oe vss dqa v ddq g nc dqb bwb adv vss nc dqa h dqb nc vss gw vss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk vss nc dqa l dqb nc vss nc bwa dqa nc m v ddq dqb vss bwe vss nc v ddq n dqb nc vss a 1 * vss dqa nc p nc dqpb vss a 0 * vss nc dqa r nc a mode v dd nc a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 synchronous chip select bw x (x=a,b) synchronous byte write controls bwe byte write enable symbol pin name oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqa-dqb data inputs/outputs dqpa-pb output power supply v dd power supply v ddq output power supply vss ground
6 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a pin descriptions 165 pbga package pin configuration 256k x 36 (top view) note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 bwe adsc adv a nc b nc a ce2 bwd bwa clk gw oe adsp a nc c dqpc nc v ddq vss vss vss vss vss v ddq nc dqpb d dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb e dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb f dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb g dqc dqc v ddq v dd vss vss vss v dd v ddq dqb dqb h nc vss nc v dd vss vss vss v dd nc nc zz j dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a k dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a l dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a m dqd dqd v ddq v dd vss vss vss v dd v ddq dq a dq a n dqpd nc v ddq vss nc nc nc vss v ddq nc dqpa p nc nc a a tdi a 1 * tdo a a a a r mode nc a a tms a 0 * tck a a a a symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bw x (x=a,b,c,d) synchronous byte write controls symbol pin name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqx data inputs/outputs dqpx data inputs/outputs v dd 3.3v/2.5v power supply v ddq isolated output power supply 3.3v /2.5v vss ground
integrated silicon solution, inc. 7 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a note: * a 0 and a 1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. 165 pbga package pin configuration 512k x 18 (top view) pin descriptions 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwb nc ce2 bwe adsc adv a a b nc a ce2 nc bwa clk gw oe adsp a nc c nc nc v ddq vss vss vss vss vss v ddq nc dqpa d nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa e nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa f nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa g nc dqb v ddq v dd vss vss vss v dd v ddq nc dqa h nc vss nc v dd vss vss vss v dd nc nc zz j dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc k dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc l dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc m dqb nc v ddq v dd vss vss vss v dd v ddq dq a nc n dqpb nc v ddq vss nc nc nc vss v ddq nc nc p nc nc a a tdi a 1 * tdo a a a a r mode nc a a tms a 0 * tck a a a a symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance adsp address status processor adsc address status controller gw global write enable clk synchronous clock ce , ce2 , ce2 synchronous chip select bw x (x=a,b) synchronous byte write controls symbol pin name bwe byte write enable oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi nc no connect dqx data inputs/outputs dqpx data inputs/outputs v dd 3.3v/2.5v power supply v ddq isolated output power supply 3.3v/2.5v vss ground
8 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a dqpb dqb dqb vddq vss dqb dqb dqb dqb vss vddq dqb dqb vss nc vdd zz dqa dqa vddq vss dqa dqa dqa dqa vss vddq dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a dqpc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc a a a a a a a a 46 47 48 49 50 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2 , ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpd parity data input/output gw synchronous global write enable mode burst sequence mode selection oe output enable v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v vss ground zz snooze enable pin configuration (3 chip-enable option) 100-pin tqfp (256k x 36) dqpb dqb dqb v dd q vss dqb dqb dqb dqb vss v dd q dqb dqb vss nc v dd zz dqa dqa v dd q vss dqa dqa dqa dqa vss v dd q dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa a v dd vss clk gw bwe oe adsc adsp adv a a dqpc dqc dqc v dd q vss dqc dqc dqc dqc vss v dd q dqc dqc nc v dd nc vss dqd dqd v dd q vss dqd dqd dqd dqd vss v dd q dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 46 47 48 49 50 (2 chip-enable option)
integrated silicon solution, inc. 9 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a nc dqb dqb vdd q vss dqb dqb dqb dqb vss vdd q dqb dqb vss nc vdd zz dqa dqa vdd q vss dqa dqa dqa dqa vss vdd q dqa dqa nc a a ce ce2 bwd bwc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc dqc dqc vddq vss dqc dqc dqc dqc vss vddq dqc dqc nc vdd nc vss dqd dqd vddq vss dqd dqd dqd dqd vss vddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc a a a a a a a a 46 47 48 49 50 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2 , ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output gw synchronous global write enable mode burst sequence mode selection oe output enable v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v vss ground zz snooze enable pin configuration (3 chip-enable option) 100-pin tqfp (256k x 32)
10 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a pin configuration (3 chip-enable option) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqb synchronous data input/output dqpa-dqpb parity data i/o; dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 gw synchronous global write enable mode burst sequence mode selection oe output enable v dd 3.3v/2.5v power supply v ddq isolated output buffer supply: 3.3v/2.5v vss ground zz snooze enable 100-pin tqfp (512k x 18) a nc nc vddq vss nc dqpa dqa dqa vss vddq dqa dqa vss nc vdd zz dqa dqa vddq vss dqa dqa nc nc vss vddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 vdd vss clk gw bwe oe adsc adsp adv a a nc nc nc vddq vss nc nc dqb dqb vss vddq dqb dqb nc vdd nc vss dqb dqb vddq vss dqb dqb dqpb nc vss vddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss vdd nc a a a a a a a a 46 47 48 49 50 (2 chip-enable option) a nc nc v ddq vss nc dqpa dqa dqa vss v ddq dqa dqa vss nc v dd zz dqa dqa v ddq vss dqa dqa nc nc vss v ddq nc nc nc a a ce ce2 nc nc bwb bwa a v dd vss clk gw bwe oe adsc adsp adv a a nc nc nc v ddq vss nc nc dqb dqb vss v ddq dqb dqb nc v dd nc vss dqb dqb v ddq vss dqb dqb dqpb nc vss v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 46 47 48 49 50
integrated silicon solution, inc. 11 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a partial truth table fu nction gw bwe bwa bwb bwc bwd read h h x x x x read h l h h h h write byte 1 h l l h h h write all bytes h l l l l l write all bytes l x x x x x truth table (1-8) operation address ce ce2 ce2 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: 1. x means dont care. h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa-d ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqas and dqpa. bwb enables writes to dqbs and dqpb. bwc enables writes to dqcs and dqpc. bwd enables writes to dqds and dqpd. dqpa and dqpb are available on the x18 version. dqpa-dqpd are avail - able on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarifcation.
12 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a interleaved burst address table (mode = v dd or no connect ) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = vss ) 0,0 1,0 0,1 a1', a0' = 1,1 absolute maximum ratings (1) symbol parameter value unit t stg storage temperature C55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to vss for i/o pins C0.5 to v ddq + 0.5 v v in voltage relative to vss for C0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to vss C0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma - nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric felds; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
integrated silicon solution, inc. 13 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a operating range (is61lpsxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v + 5% 3.3v / 2.5v + 5% industrial C40c to +85c 3.3v + 5% 3.3v / 2.5v + 5% operating range (is61vpsxxxxx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v + 5% 2.5v + 5% industrial C40c to +85c 2.5v + 5% 2.5v + 5% dc electrical characteristics (over operating range) 3.3v 2.5v symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = C4.0 ma (3.3v) 2.4 2.0 v i oh = C1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) 0.4 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage -0.3 0.8 -0.3 0.7 v i li input leakage current vss v in v dd (1) -5 5 -5 5 a i lo output leakage current vss v out v ddq , -5 5 -5 5 a oe = v ih operating range (is64lpsxxxxx) range ambient temperature v dd v ddq automotive C40c to +125c 3.3v + 5% 3.3v / 2.5v + 5%
14 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a power supply characteristics (1) (over operating range) -250 -200 -166 max max max symbol parameter test conditions temp. range x18 x36 x18 x36 x18 x36 uni t i cc ac operating device selected, com. 275 275 250 250 225 225 ma supply current oe = v ih , zz v il , i nd . 300 300 275 275 250 250 all inputs 0.2v or auto. 300 300 v dd C 0.2v, cycle time t kc min. i sb standby current device deselected, com. 150 150 150 150 150 150 ma ttl input v dd = max., ind. 150 150 150 150 150 150 all inputs v il or v ih , a u to . 200 200 zz v il , f = max. i sbi standby current device deselected, com. 100 100 100 100 100 100 m a c mos input v dd = max., ind. 105 105 105 105 105 105 v in d v ss + 0.2v or auto. 130 130 t v dd C 0.2v f = 0 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100a maximum leakage current when tied to v ss + 0.2v or v dd C 0.2v.
integrated silicon solution, inc. 15 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 3.3v. 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and refe rence level output load see figures 1 and 2 ac test loads figure 2 317 5 pf including jig and scope 351 output 3.3v figure 1 output z o = 50 1.5v 50
16 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 2.5 i/o output load equivalent figure 4 1,667 5 pf including jig and scope 1,538 output 2.5v figure 3 output z o = 50 1.25v 50
integrated silicon solution, inc. 17 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a read/write cycle switching characteristics (over operating range) -250 -200 -166 symbol parameter min. max. min. max. min. max. unit f max clock frequency 250 200 166 mhz t kc cycle time 4.0 5 6 ns t kh clock high time 1.7 2 2.4 ns t kl clock low time 1.7 2 2.3 ns t kq clock access time 2.6 3.1 3.8 ns t kqx (2) clock high to output invalid 0.8 1.5 1.5 ns t kqlz (2,3) clock high to output low-z 0.8 1 1.5 ns t kqhz (2,3) clock high to output high-z 2.6 3.0 3.5 ns t oeq output enable to output valid 2.6 3.1 3.5 ns t oelz (2,3) output enable to output low-z 0 0 0 ns t oehz (2,3) output disable to output high-z 2.6 3.0 3.5 ns t as address setup time 1.2 1.4 1.7 ns t ws read/write setup time 1.2 1.4 1.7 ns t ces chip enable setup time 1.2 1.4 1.7 ns t av s address advance setup time 1.2 1.4 1.7 ns t ds data setup time 1.2 1.4 1.7 ns t ah address hold time 0.3 0.4 0.7 ns t wh write hold time 0.3 0.4 0.7 ns t ceh chip enable hold time 0.3 0.4 0.7 ns t av h address advance hold time 0.3 0.4 0.7 ns t dh data hold time 0.3 0.4 0.7 ns t pds zz high to power down 2 2 2 cyc t pus zz low to power down 2 2 2 cyc note: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
18 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
integrated silicon solution, inc. 19 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a write cycle timing single write data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk wr1w r2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1w r2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr 2 write 2c 2d 2a 2b
20 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z snooze mode electrical characteristics symbol parameter conditions temperature min. max. unit range i sb 2 current during snooze mode zz vih com. 50 ma ind. 60 auto. 75 t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to snooze current 2 cycle t rzzi zz inactive to exit snooze current 0 ns
integrated silicon solution, inc. 21 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a ieee 1149.1 serial boundary scan (jtag) the is61lps/vpsxxxxxx products have a serial boundary scan test access port (tap) in the pbga package only. (the tqfp package not available.) this port operates in accordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specifcation are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not confict with the performance of other devices us - ing 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any regis - ter. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an applica - tion. tdi is connected to the most signifcant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram
22 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the ta p state machine (see ta p controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least signifcant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for fve rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the in - struction register. this register is loaded when it is placed between the tdi and tdo pins. (see ta p controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least signifcant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass reg - ister is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 confguration has a 75-bit-long register and the x18 confguration also has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed be - tween the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identifcation (id) register the id register is loaded with a vendor-specifc, 32-bit code during the capture-dr state when the idcode com - mand is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identifcation register defnitions table. scan register sizes register bit size bit size name (x18) (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 75 75 identification register definitions instruction field description 256k x 36 512k x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defnes depth of sram. 256k or 512k 00111 01000 device width (22:18) defnes width of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identifcation of sram vendor. 00011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1
integrated silicon solution, inc. 23 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other fve instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buf - fers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/ preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instruc - tions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap control - ler must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instruc - tions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specifc, 32- bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded to the instruc - tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock oper - ates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controllers capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the ta p into the update to the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruc - tion register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
24 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register be - tween the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram
integrated silicon solution, inc. 25 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a tap electrical characteristics over the operating range (1,2) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = C2.0 ma 1.7 v v oh 2 output high voltage i oh = C100 a 2.1 v v ol 1 output low voltage i ol = 2.0 ma 0.7 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage C0.3 0.7 v i x input leakage current v ss v i v ddq C10 10 a notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot: v il (ac) -1.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ac electrical characteristics (1,2) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ns f tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns t tmss tms setup to tck clock rise 10 ns t tdis tdi setup to tck clock rise 10 ns t cs capture setup to tck rise 10 ns t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns t td ov tck low to tdo valid 20 ns t tdo x tck low to tdo invalid 0 ns notes: 1. both t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. test conditions are specifed using the load in tap ac test conditions. t r /t f = 1 ns.
26 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a don't care undefined tck tms tdi tdo t thtl t tl th t thth t mvth t thmx t d vth t thdx 1 2 3 4 5 6 t tlo x t tlo v tap timing 20 pf tdo gnd 50 vtrig z 0 = 50 tap output load equivalent tap ac test conditions (2.5v/3.3v) input pulse levels 0 to 2.5v/0 to 3.0v input rise and fall times 1ns input timing reference levels 1.25v/1.5v output reference levels 1.25v/1.5v test load termination supply voltage 1.25v/1.5v vtrig 1.25v/1.5v
integrated silicon solution, inc. 27 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 119 bga boundary scan order (256k x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 19 dqb 7g 37 bwa 5l 55 dqd 2k 2 a 3t 20 dqb 6f 38 bwb 5g 56 dqd 1l 3 a 4t 21 dqb 7e 39 bwc 3g 57 dqd 2m 4 a 5t 22 dqb 7d 40 bwd 3l 58 dqd 1n 5 a 6r 23 dqb 7h 41 ce2 2b 59 dqd 1p 6 a 3b 24 dqb 6g 42 ce 4e 60 dqd 1k 7 a 5b 25 dqb 6e 43 a 3a 61 dqd 2l 8 dqa 6p 26 dqb 6d 44 a 2a 62 dqd 2n 9 dqa 7n 27 a 6a 45 dqc 2d 63 dqd 2p 10 dqa 6m 28 a 5a 46 dqc 1e 64 mode 3r 11 dqa 7l 29 adv 4g 47 dqc 2f 65 a 2c 12 dqa 6k 30 adsp 4a 48 dqc 1g 66 a 3c 13 dqa 7p 31 adsc 4b 49 dqc 2h 67 a 5c 14 dqa 6n 32 oe 4f 50 dqc 1d 68 a 6c 15 dqa 6l 33 bwe 4m 51 dqc 2e 69 a1 4n 16 dqa 7k 34 gw 4h 52 dqc 2g 70 a0 4p 17 zz 7t 35 clk 4k 53 dqc 1h 18 dqb 6h 36 a 6b 54 nc 5r 119 bga boundary scan order (512k x 18) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 14 dqa 7g 27 clk 4k 40 dqb 2k 2 a 2t 15 dqa 6f 28 a 6b 41 dqb 1l 3 a 3t 16 dqa 7e 29 bwa 5l 42 dqb 2m 4 a 5t 17 dqa 6d 30 bwb 3g 43 dqb 1n 5 a 6r 18 a 6t 31 ce2 2b 44 dqb 2p 6 a 3b 19 a 6a 32 ce 4e 45 mode 3r 7 a 5b 20 a 5a 33 a 3a 46 a 2c 8 dqa 7p 21 adv 4g 34 a 2a 47 a 3c 9 dqa 6n 22 adsp 4a 35 dqb 1d 48 a 5c 10 dqa 6l 23 adsc 4b 36 dqb 2e 49 a 6c 11 dqa 7k 24 oe 4f 37 dqb 2g 50 a1 4n 12 zz 7t 25 bwe 4m 38 dqb 1h 51 a0 4p 13 dqa 6h 26 gw 4h 39 nc 5r
28 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 165 pbga boundary scan order ( x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 mode 1r 21 dqb 11g 41 nc 1a 61 dqd 1j 2 nc 6n 22 dqb 11f 42 ce 2 6a 62 dqd 1k 3 a 11p 23 dqb 11e 43 bw a 5b 63 dqd 1l 4 a 8p 24 dqb 11d 44 bw b 5a 64 dqd 1m 5 a 8r 25 dqb 10g 45 bw c 4a 65 dqd 2j 6 a 9r 26 dqb 10f 46 bw d 4b 66 dqd 2k 7 a 9p 27 dqb 10e 47 ce2 3b 67 dqd 2l 8 a 10p 28 dqb 10d 48 ce 3a 68 dqd 2m 9 a 10r 29 dqb 11c 49 a 2a 69 dqd 1n 10 a 11r 30 nc 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 dqa 11n 32 a 10b 52 dqc 1c 72 a 4r 13 dqa 11m 33 adv 9a 53 dqc 1d 73 a 4p 14 dqa 11l 34 adsp 9b 54 dqc 1e 74 a1 6p 15 dqa 11k 35 adsc 8a 55 dqc 1f 75 a0 6r 16 dqa 11j 36 oe 8b 56 dqc 1g 17 dqa 10m 37 bwe 7a 57 dqc 2d 18 dqa 10l 38 gw 7b 58 dqc 2e 19 dqa 10k 39 clk 6b 59 dqc 2f 20 dqa 10j 40 nc 11b 60 dqc 2g
integrated silicon solution, inc. 29 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 165 pbga boundary scan order ( x 18) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 mode 1r 21 dqa 11g 41 nc 1a 61 dqb 1j 2 nc 6n 22 dqa 11f 42 ce 2 6a 62 dqb 1k 3 a 11p 23 dqa 11e 43 bw a 5b 63 dqb 1l 4 a 8p 24 dqa 11d 44 nc 5a 64 dqb 1m 5 a 8r 25 dqa 11c 45 bw b 4a 65 dqb 1n 6 a 9r 26 nc 10f 46 nc 4b 66 nc 2k 7 a 9p 27 nc 10e 47 ce2 3b 67 nc 2l 8 a 10p 28 nc 10d 48 ce 3a 68 nc 2m 9 a 10r 29 nc 10g 49 a 2a 69 nc 2j 10 a 11r 30 a 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 nc 11n 32 a 10b 52 nc 1c 72 a 4r 13 nc 11m 33 adv 9a 53 nc 1d 73 a 4p 14 nc 11l 34 adsp 9b 54 nc 1e 74 a1 6p 15 nc 11k 35 adsc 8a 55 nc 1f 75 a0 6r 16 nc 11j 36 oe 8b 56 nc 1g 17 dqa 10m 37 bwe 7a 57 dqb 2d 18 dqa 10l 38 gw 7b 58 dqb 2e 19 dqa 10k 39 clk 6b 59 dqb 2f 20 dqa 10j 40 nc 11b 60 dqb 2g
30 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a ordering information (3.3v core/2.5v-3.3v i/o) commercial range: 0c to +70c confguration frequency order part number package (1) 256kx36 250 is61lps25636a-250tq 100 tqfp, 3ce is61lps25636a-250b2 119 pbga is61lps25636a-250b3 165 pbga 200 is61lps25636a-200tq 100 tqfp, 3ce is61lps25636a-200b2 119 pbga is61lps25636a-200b3 165 pbga 166 is61lps25636a-166tq 100 tqfp, 3ce is61lps25636a-166tql 100 tqfp, 3ce, lead-free 512kx18 250 IS61LPS51218A-250tq 100 tqfp, 3ce IS61LPS51218A-250b2 119 pbga IS61LPS51218A-250b3 165 pbga 200 IS61LPS51218A-200tq 100 tqfp, 3ce IS61LPS51218A-200b2 119 pbga IS61LPS51218A-200b3 165 pbga
integrated silicon solution, inc. 31 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a industrial range: -40c to +85c confguration frequency order part number package (1) 256kx32 200 is61lps25632a-200tqli 100 tqfp, 3ce, lead-free 256kx36 250 is61lps25636a-250tqi 100 tqfp, 3ce is61lps25636a-250tqli 100 tqfp, 3ce, lead-free is61lps25636a-250b2i 119 pbga is61lps25636a-250b3i 165 pbga 200 is61lps25636a-200tqi 100 tqfp, 3ce is61lps25636a-200tq2li 100 tqfp, 2ce, lead-free is61lps25636a-200tq2i 100 tqfp, 2ce is61lps25636a-200tqli 100 tqfp, 3ce, lead-free is61lps25636a-200b2i 119 pbga is61lps25636a-200b2li 119 pbga, lead-free is61lps25636a-200b3i 165 pbga is61lps25636a-200b3li 165 pbga, lead-free 166 is61lps25636a-166tqli 100 tqfp, 3ce, lead-free 512kx18 250 IS61LPS51218A-250tqi 100 tqfp, 3ce IS61LPS51218A-250b2i 119 pbga IS61LPS51218A-250b3i 165 pbga 200 IS61LPS51218A-200tqi 100 tqfp, 3ce IS61LPS51218A-200tq2li 100 tqfp, 2ce, lead-free IS61LPS51218A-200tq2i 100 tqfp, 2ce IS61LPS51218A-200tqli 100 tqfp, 3ce, lead-free IS61LPS51218A-200b2i 119 pbga IS61LPS51218A-200b3i 165 pbga note: 1. for 100 tqfp, 2ce option contact sram marketing at sram@issi.com automotive range: -40c to +125c confguration frequency order part number package 256kx36 166 is64lps25636a-166tqla3 100 tqfp, 3ce
32 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a ordering information (2.5v core/2.5v i/o) commercial range: 0c to +70c confguration frequency order part number package (1) 256kx36 250 is61vps25636a-250tq 100 tqfp, 3ce is61vps25636a-250b2 119 pbga is61vps25636a-250b3 165 pbga 200 is61vps25636a-200tq 100 tqfp, 3ce is61vps25636a-200b2 119 pbga is61vps25636a-200b3 165 pbga 512kx18 250 is61vps51218a-250tq 100 tqfp, 3ce is61vps51218a-250b2 119 pbga is61vps51218a-250b3 165 pbga 200 is61vps51218a-200tq 100 tqfp, 3ce is61vps51218a-200b2 119 pbga is61vps51218a-200b3 165 pbga industrial range: -40c to +85c confguration frequency order part number package (1) 256kx36 250 is61vps25636a-250tqi 100 tqfp, 3ce is61vps25636a-250b2i 119 pbga is61vps25636a-250b3i 165 pbga 200 is61vps25636a-200tqi 100 tqfp, 3ce is61vps25636a-200tq2i 100 tqfp, 2ce is61vps25636a-200tqli 100 tqfp, 3ce, lead-free is61vps25636a-200b2i 119 pbga is61vps25636a-200b3i 165 pbga 512kx18 250 is61vps51218a-250tqi 100 tqfp, 3ce is61vps51218a-250b2i 119 pbga is61vps51218a-250b3i 165 pbga 200 is61vps51218a-200tqi 100 tqfp, 3ce is61vps51218a-200tq2i 100 tqfp, 2ce is61vps51218a-200b2i 119 pbga is61vps51218a-200b3i 165 pbga note: 1. for 100 tqfp, 2ce option contact sram marketing at sram@issi.com
integrated silicon solution, inc. 33 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a
34 integrated silicon solution, inc. rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 1. controlling dimension : mm . note : 2. reference document : jedec ms-028 10/02/2008 package outline
integrated silicon solution, inc. 35 rev. l 09/06/12 i s61lps51218a, is61lps25636a, is61lps25632a, is64lps25636a, is61vps51218a, is61vps25636 a 1. controlling dimension : mm . note : package outline 08/28/2008

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